Course Administration

Course reading materials, lecture videos, messages and grades will be handled using the Canvas platform. Please use Canvas Messages (not email) to contact the instructor.

Assignments are grouped in a recommended weekly schedule. Planned lab assignments will comprise about 2/3 of the course. The last 1/3 will be devoted to student design projects.

There is room in the schedule to fall behind slightly on the assignments. Any assignment can be submitted up to 1 week late with no penalty. There will be a 10% penalty after 1 week, and a 20% penalty after 3 weeks. Course grades will be finalized on the last day of finals week (4/30), so everything needs to be submitted before that date.

Lab Procedures and Materials

Please see the Workflow Document for full details on laboratory procedures.

All assigned work for this course is laboratory in nature. At minimum, you will need:

• Digilent Basys3 FPGA board (available from the ECE store)
• Access to a computer with a terminal emulator

Most of our work will be running simulations. The hardware tasks usually go quickly, so you can share a Basys3 board with other students if you’re unable to obtain one.

Assignment Groups:

1. Verilog Syntax and Best Practices
   1. Modules
      1. Simple Module [files]
      2. Build Procedure [files]
      3. Parameters [files]
      4. Tasks [files]
      5. Functions [files]
   2. Operations
      1. Unary Operators [files]
      2. Bitwise Operators [files]
      3. Logical Operators [files]
      4. Unsigned Arithmetic [files]
      5. Signed Arithmetic [files]
   3. Loops and Conditionals
      1. For Loops [files]
      2. While Loops [files]
      3. Generate Loops [files]
      4. Case Statements [files]
      5. Conditional Operator [files]
2. RTL Design Concepts
   1. State Machines
      1. Keypad Interface [files]
      2. Debouncer [files]
      3. Handshaking [files]
   2. Communication Protocols
      1. PWM [ files ]
      2. SPI READ interface [ files ]
   3. Memory
      1. Random Access Memory [ files ]
      2. Sin Lookup Table (LUT) [ files ]
      3. FIFOs, LIFOs, Stacks, Queues [ files ]
3. Final Project
   1. Proposal
   2. Specification
   3. Milestone
   4. Final Demonstration