Compact Conditional Operators

Many Verilog designs make use of a compact conditional operator:

wire q;

assign q = <condition> ? <if-true> : <else>; 

A comman example, shown below, is an “enable” mask. Suppose there is some internal signal named a. When enabled by en==1, the module assigns q = a, otherwise it assigns q = 0:

assign q = en ? a : 0;

The syntax is also permitted in always blocks:

reg q;

always @(*) begin
   q = en ?  a : 0;
end

Assigned Tasks

This assignment uses only a testbench simulation, with no module to implement. Open the file src/testbench.v and examine how it is organized. It uses the conditional operator in an always block to assign q = a^b (XOR) when enabled, else q=0.

Run make simulate to test the operation. Verify that the console output is correct. Then modify the testbench to use an assign statement instead of an always block. Change the type of q as appropriate for the assign statement.

Turn in your work using git:

git add  *.txt 
git commit . -m "Complete"
git push origin main

Indicate on Canvas that your assignment is done.