Logical Operators

Logical Operators in Verilog

Verilog supports logical operations for conditional statements about vectors. Logical operators look very similar to bitwise operators, but their function is quite different. Each logical operator returns a TRUE/FALSE result, with these possible operations:

Operator	Explanation
`a && b`	`a` is non-zero AND `b` is non-zero
`a \|\| b`	`a` is non-zero OR `b` is non-zero
`a == b`	All bits of `a` match corresponding bits in `b`
`a != b`	At least one bit from `a` doesn’t match the corresponding bit in `b`

A vector is non-zero if any of its bits are 1. If logical operations are applied to vectors, they can sometimes be hard to interpret. For example, a && b means “at least one of the bits in a are 1 AND at least one of the bits in b is 1”. To avoid creating confusion, the best practice is use && and || only on TRUE/FALSE conditions, like this:

if ((a == b) && (b != c))
   // Do something

In this example, (a == b) returns a TRUE/FALSE result, and (b != c) returns a TRUE/FALSE result. Then the logical AND operator && has a simple interpretation, “both of these conditions are TRUE”.

Run make to see the example cases.

Assigned Tasks

Modify src/testbench.v with the following changes:

Just before the last $write line, insert an if condition:

   if ((a[3] == b[3]) && (a[2] != b[2]) || (|a == 0))
      $write(" condition met ");

Put the same condition before the final $fwrite line, and change the conditional $write statement to $fwrite.

Carefully consider how to interpret the condition. Run make to simulate the modified testbench and confirm each line where the condition is met.

When finished, turn in your work using git:

git add test_result.txt
git commit . -m "Completed"
git push origin main

Then indicate on Canvas that your work is done.