This paper, led by our collaborators at the ETIS lab in France, represents our latest work in probabilistic bit-flipping algorithms for Low-Density Parity-Check (LDPC) codes used in telecommunications and solid-state memory applications. The paper has been accepted to appear in a future issue of the journal, and is now available via IEEE Early Access.
#^A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes - IEEE Journals & MagazineThis paper presents a new bit flipping (BF) decoder, called the probabilistic parallel BF (PPBF) for low-density parity-check codes on the binary symmetric channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to significantly improve the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in Section II. The application-specific integrated circuit synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.
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