| Name | Last modified | Size | Description | |
|---|---|---|---|---|
| Parent Directory | - | |||
| 5_final/ | 2026-01-05 20:27 | - | ||
| 4_midterm/ | 2026-01-05 20:27 | - | ||
| 3_digital_systems/ | 2026-01-05 20:27 | - | ||
| 2_rtl/ | 2026-01-05 20:27 | - | ||
| 0_terminal_basics/ | 2026-01-05 20:27 | - | ||
| 0_gitting_started/ | 2026-01-05 20:27 | - | ||
| 1_verilog/ | 2025-12-27 19:00 | - | ||