Index of /courses/3700/assignments/1_verilog/1_modules/2_build

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[DIR]figures/2025-12-26 22:55 -  
[DIR]src/2025-12-26 22:55 -  
[   ]Makefile2026-01-05 20:27 374  
[TXT]build.tcl2026-01-05 20:27 474  
[   ]simple_module.xdc2026-01-05 20:27 744  
[TXT]assigned_tasks.md2026-01-05 20:27 19K 
[TXT]assigned_tasks.html2026-01-05 20:27 41K 

Apache/2.4.58 (Ubuntu) Server at left.engr.usu.edu Port 443