Course Administration

Course reading materials, lecture videos, messages and grades will be handled using the Canvas platform. Please use Canvas Messages (not email) to contact the instructor.

Assignments are grouped in a recommended weekly schedule. Planned lab assignments will comprise about 1/2 of the course. The second 1/2 will be devoted to midterm and final design projects. Regular lectures will be given during the first half of the course, and during the second half class time will mainly be used for design discussions and programming assistance.

There is room in the schedule to fall behind slightly on the assignments. Any assignment can be submitted up to 1 week late with no penalty. There will be a 10% penalty after 1 week, and a 20% penalty after 3 weeks. Course grades will be finalized on the last day of finals week, so everything needs to be submitted before that date.

Lab Procedures and Materials

Please see the Workflow Document for full details on laboratory procedures.

All assigned work for this course is laboratory in nature. At minimum, you will need:

• Digilent Basys3 FPGA board (available from the ECE store)
• Access to a computer with a terminal emulator

Most of our work will be running simulations. The hardware tasks usually go quickly, so you can share a Basys3 board with other students if you’re unable to obtain one.

Textbook

This course uses the Digital Logic textbook by Brown and Vranesic. You can access the textbook within Canvas using the Bookshelf tab. This is the same textbook used in the ECE 2700 course, and will be useful as a companion to the assignments and lecture topics.

Assignment Groups:

0. Introductory Tutorials
   1. Terminal Basics
   2. Gitting Started
1. Verilog Syntax and Best Practices
   1. Modules
      1. Simple Module [files]
      2. Build Procedure [files]
      3. Parameters [files]
      4. Tasks [files]
      5. Functions [files]
   2. Operations
      1. Unary Operators [files]
      2. Bitwise Operators [files]
      3. Logical Operators [files]
      4. Unsigned Arithmetic [files]
      5. Signed Arithmetic [files]
   3. Loops and Conditionals
      1. For Loops [files]
      2. While Loops [files]
      3. Generate Loops [files]
      4. Case Statements [files]
      5. Conditional Operator [files]
2. RTL Design Concepts
   1. State Machines
      1. Keypad Interface [files]
      2. Debouncer [files]
      3. Handshaking [files]
      4. Serial Interface [files]
   2. Communication Protocols
      1. PWM [ files ]
      2. SPI READ interface [ files ]
   3. Memory
      1. Random Access Memory [ files ]
      2. Sin Lookup Table (assignments/LUT) [ files ]
      3. FIFOs, LIFOs, Stacks, Queues [ files ]
3. Midterm Project
4. Final Project
   1. Proposal
   2. Specification
   3. Milestone
   4. Final Demonstration